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ISL267817
6
FN7877.2
April 19, 2012
tdDO
DCLOCK Falling Edge to Next DOUT Valid
35
150
ns
tDIS
CS/SHDN Rising Edge to DOUT Disable Time
See Note 10
40
50
ns
tEN
DCLOCK Falling Edge to DOUT Enabled
22
100
ns
tf
DCLOCK Fall Time
1
100
ns
tr
DCLOCK Rise Time
1
100
ns
NOTE:
10. During characterization, tDIS is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the ADS7817 loading
(3k, 100pF) is calculated.
Timing Specifications Limits established by characterization and are not production tested. +VCC = 5V, fDCLOCK =3.2MHz, fS = 200kSPS,
VREF =2.5V; VCM = VREF. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM
NOTES:
11. After completing the data transfer, additional clocks applied while CS/SHDN is low will result in the previous data being retransmitted LSB-first,
followed by indefinite transmission of zeros.
12. After completing the data transfer, additional clocks applied while CS/SHDN is low will result in indefinite transmission of zeros.
tSUCS
B10
B9
B8
B7
B6B5B4B3B2
B1
B0
B11
B10
B9B8
NULL
BIT
Hi-Z
NULL
BIT
CS/SHDN
DCLOCK
DOUT
tCSD
tCYC
POWER
DOWN
tSMPL
tCONV
tDATA
tSUCS
B10
B9B8B7B6
B5
B4
B3
B2B1B0
B11
B10
B9
B8
NULL
BIT
Hi-Z
CS/SHDN
DCLOCK
DOUT
tCSD
tCYC
POWER
DOWN
tSMPL
tCONV
tDATA
B1
B2
B3
B4
B5
B7
B6
B11
(MSB)
B11
(MSB)
Note 12
Note 11
FIGURE 4. EQUIVALENT LOAD CIRCUIT
OUTPUT
PIN
CL
10pF
+VCC
2.85k
RL
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